VLSI chips design is becoming increasingly complex and calling for more and more automation. Many chip design problems can be formulated as constraint problems and are potentially amenable to CP techniques. To the best of our knowledge, though, there has been little CP work in this domain to date. We describe a successful application of a CP based tool to a particular pin-assignment problem in which tens of thousands of pins (i.e., connection points) belonging to internal units on the chip must be placed within their units so as to satisfy certain constraints and optimize the wirability of the design. Our tool has been tested on real IBM designs and is now being integrated into IBM’s chip development environment.